1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming stressed silicon-carbon areas in an NMOS transistor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions source/drain regions.
Device designers are under constant pressure to improve the electrical performance characteristics of semiconductor devices, such as transistors, and the overall performance capabilities of integrated circuit devices that incorporate such devices. One technique that has been and continues to be employed to improve the performance of such transistors is to reduce or scale the channel length of such transistors. As device dimensions have decreased, device designers have resorted to other techniques to improve device performance. One such method involves the use of channel stress engineering techniques on transistors to create a tensile stress in the channel region for NMOS transistors and to create a compressive stress in the channel region for PMOS transistors. These stress conditions improve charge carrier mobility of the devices—electrons for NMOS devices and holes for PMOS devices. Additional stress engineering techniques for PMOS transistors may also involve the formation of eptaxially-deposited silicon-germanium source/drain regions, and the formation of an epitaxially-deposited silicon-germanium layer under in the channel region of the PMOS device. Additional stress engineering techniques that have been performed on NMOS transistors includes the formation of silicon-carbon source-drain regions to induce a desired tensile stress in the channel region of the NMOS transistor, as discussed more fully below.
One illustrative prior art technique for forming silicon-carbon, tensile stress-inducing regions in an NMOS transistor will now be described with reference to FIGS. 1A-1C. FIG. 1A depicts an illustrative NMOS transistor 30 at an early stage of fabrication wherein a gate electrode structure 14 has been formed above a semiconducting substrate 10 in an active region that is defined by a shallow trench isolation structure 12. The gate electrode structure 14 typically includes a gate insulation layer 14A and a conductive gate electrode 14B. An illustrative gate cap layer 15 is formed above the gate electrode 14B, and illustrative sidewall spacers 18 are also formed proximate the gate electrode structure 14. To arrive at the structure depicted in FIG. 1A, the gate electrode structure 14 and the gate cap layer 15 are typically formed by depositing various layers of material and performing one or more etching processes to define the basic stack of materials shown in FIG. 1A. Thereafter, an initial ion implantation process is typically performed to form so-called extension implant regions 16 in the substrate 10. Then, the sidewall spacers 18 are formed proximate the gate electrode structure 14 by depositing a layer of spacer material and thereafter performing an anisotropic etching process. After the spacers 18 are formed, a second ion implantation process is then performed on the transistor 30 to form so-called deep source-drain implant regions 20 in the substrate 10. The ion implantation process performed to form the deep source-drain implant regions 20 is typically performed using a higher dopant dose and it is performed at higher implant energy than the ion implantation process that was performed to form the extension implant regions 16. The above referenced implantation processes are performed using N-type dopants for the NMOS transistor 30. Other implant regions, such as so-called halo implant regions (not shown) have also been formed in the substrate 10 at the point of fabrication depicted in FIG. 1A. Thereafter, as shown in FIG. 1A, an ion implantation process 23 is performed to amorphize at least a portion of the area of the substrate 10 where the final source drain regions of the transistor 30 will be formed. This amorphization implant process 23 may be performed using xenon, germanium, etc. ions at a dose and energy level to sufficient to cause damage to the lattice structure of the substrate 10 in an effort to make the substrate 10 more receptive to carbon ions that will be subsequently implanted into the substrate 10 in the amorphized areas.
Next, as shown in FIG. 1B, an ion implantation process 25 is performed using carbon ions to implant the carbon ions in the source/drain areas of the substrate 10. The ion implant process 25 may typically be performed with a dose of 1-5 e15 atoms/cm2 carbon atoms at an energy level of approximately 1-5 keV. The various implantation processes described with respect to FIGS. 1A-1C may be performed using well-known methods, and well-known ion implantation systems.
Thereafter, as shown in FIG. 1C, a heating or anneal process 27 is performed to form the final source drain regions 29 for the NMOS transistor 30 that are comprised of, at least in part, silicon-carbon material. The heating process 27 repairs the damage to the lattice structure of the substrate material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted carbon and N-type dopant materials are incorporated into the silicon lattice.
Another illustrative prior art technique for forming silicon-carbon, tensile stress-inducing regions in an NMOS transistor will now be described with reference to FIGS. 2A-2C. FIG. 2A depicts the illustrative NMOS transistor 30 at an early stage of fabrication, wherein the gate electrode structure 14 has been formed above the semiconducting substrate 10. As noted previously, the gate electrode structure 14 typically includes a gate insulation layer 14A and a conductive gate electrode 14B. An illustrative gate cap layer 15 is formed above the gate electrode 14B, and illustrative sidewall spacers 18 are also formed proximate the gate electrode structure 14, just as described above with reference to FIGS. 1A-1C. An illustrative extension implant region 32 that is formed in the substrate 10 is also depicted in FIG. 2A. As discussed previously with respect to FIGS. 1A-1C, to arrive at the structure depicted in FIG. 2A, the gate electrode structure 14 and the gate cap layer 15 are typically formed by depositing various layers of material and performing one or more etching processes to define the basic stack of materials shown in FIG. 2A. Thereafter, an initial ion implantation process with an N-type dopant, e.g., arsenic, is typically performed to form the extension implant regions 32 in the substrate 10. Other implant regions, such as so-called halo implant regions (not shown) have also be previously formed in the substrate 10 at the point of fabrication depicted in FIG. 2A. Then, the sidewall spacers 18 are formed proximate the gate electrode structure 14 by depositing a layer of spacer material and thereafter performing an anisotropic etching process.
Next, as shown in FIG. 2B, after the spacers 18 are formed, an etching process is performed to form recesses 34 in the substrate 10. The masking layer used during the etching process that is performed to define the recesses 34 is not depicted in the drawings. Then, as shown in FIG. 3C, an epitaxial deposition process is performed to form epitaxial silicon-carbon regions 36 in the cavities 34. In this technique, carbon atoms are introduced in situ during the epitaxial deposition process. After the epitaxial silicon-carbon regions 36 are formed, a second ion implantation process is then performed on the transistor 30 to form so-called deep source-drain implant regions (not shown) in the substrate 10. Thereafter, a heating or anneal process is performed to form the final source drain regions (not shown) for the NMOS transistor 30.
The tensile stress created by the silicon-carbon regions is created because a carbon atom is smaller than a silicon atom. Thus, when the carbon atoms are incorporated into the silicon lattice structure, the material exhibits a desirable tensile stress, at least a portion of which is transferred to the channel region of the NMOS transistor. Unfortunately, using the prior art techniques described above, the amount of carbon that can be introduced into the silicon material is limited, i.e., carbon content is limited to about 1-2%. Such low levels of carbon make it difficult to create a significant tensile stress level in the resulting material, thereby limiting the effectiveness of silicon-carbon material to impart the desired levels of tensile stress on the channel region of an NMOS transistor.
The present disclosure is directed to various methods of forming stressed silicon-carbon areas in an NMOS transistor device that may solve or reduce one or more of the problems identified above.